Q-factor in series

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Parallel ac networks

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 The clock shown in diagram 22.5 is running at 1 MHz in the simulation of a 3-bit up-counter. Traces show the clock from top to bottom and A,B & C shows the output. At one mega hertz clock rates or less, we may ignore the propagation delays of  few nanoseconds.

 Figure 22.6 shows the result when we increase the clock rate by ten times and outputs are also plotted on 10 time scale. The Propagation delays are of more relative importance and we can observe them in the plots. 11 ns is a typical delay interval of the 74LS73 J-K flip-flop that is used in simulation . 
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Synchoroneous Counters

If we Clock all the flip-flops at the same time it will eliminate the ripple effect. Instead of having each stage to be clocked by the output from the previous stage, they are all clocked at the same instant by the clock input signal. The figure 22.7  below demonstrates such a counter composed of from 3 J-K flip-flops. It is thus known as a synchronous counter.
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The BCD counters are not binary counters. The Binary counters divide by 2 at each stage, and their outputs run from 0 to (2n - 1), where n is the number of stages or bits. The counter 4518 shown in the fig below is an example of a decimal counter.

In one IC there are 2 distinct synchronous counters . Each counter has 4 stages. In case of counting up, its outputs run from 0000 to 1001 (0 to 9) and then repeat again. It can also perform downward count. Another beneficial feature of this counter is that it contains four inputs, each stage has one, in order to make it with a value before counting begins. We can cascade the two 4518 counters for counting from 0 to 99 in binary coded decimal.
The circuit presented in the diagram is set up for counting clockpulses. However, in this counter or others we need not to count regularly occurring pulses. It is appropriate to count pulses that have varying length and occurring at irregular intervals of time. The one use of the circuit used, for instance, might be to accept input from a photodiode detector and count supporters passing through the turnstile of a football ground.
It is to be noted that the input is going to the clock input of bothcounters. The 4518 counter possess an ENABLE input which enables to perform counting when it is made high. The EN input of counter 1 is connected permanently to the positive supply line,  making this counter to count all the time.
The outputs coming from Counter 1 are decoded by means of a 2-input AND gate. The output of the gate would be low, If the count registered on Counter 1 is between 0000 and 1000 (0 and 8). This implies that the Counter 2 can not register any counts — it is in disabled mode. When point 1001 (9) reaches for counter 1, both inputs of the AND gate are high for the first time. The coming output goes higher and enables Counter 2. Counter 1 changes to ‘0’ and Counter 2 changes to ‘1’ at the next rising edge of the clock. The output of the AND gate goes low, and Counter 2 is disabled until Counter 1 again reaches ‘9’. The graphs drawn below demonstrates the sequence as the counters begin to count from 0 to 15.
There are some other counters (for example the counter 4029). These counters have a special OUT output that goes from low to high when counter start changing from 9 to 0. This output is then fed to the clock input of the next counter and increments its count. Like the 4518 count, the 4029 counter is an up/down counter and it is also a binary/decimal counter, and this one is  of the most versatile counters available.
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Robots in Industry

In recent years the application of robots has been tremendously increased in German, American, and other developed countries. The robots are yet to be introduced in the industries of under developed countries including some Asian countries, where the work is heavily carried in manual way.

The robotics application in industry is successful for the following reasons:
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The diagram shown below demonstrates one of the simplest type of active filters. It is composed of a resistor-capacitor passive filter that is followed by a non-inverting amplifier for the purpose of restoring or possibly increasing the amplitude of the signal.

With the values that are shown in the figure, the voltage gain level of the amplifier comes out to be 1.56. Shown below is the graph that displays the signals in this filter when it is supplied with a 1 V sinusoid at 1 kHz
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