If we Clock all the flip-flops at the same time it will eliminate the ripple effect. Instead of having each stage to be clocked by the output from the previous stage, they are all clocked at the same instant by the clock input signal. The figure 22.7 below demonstrates such a counter composed of from 3 J-K flip-flops. It is thus known as a synchronous counter.
The inputs for J and K of the first flip-flop are kept higher, just as in the ripple counter, but the J and K inputs of up-coming flip-flops are connected to the Q output of the previous stage. The plots shown below show us the output of the synchronous counter, plotted with the same clock speed and time scale as shoen in Figure 22.10 at the end of this tutorial.
Still presents there an 11 ns delay between the clock tending to be low and the variations in the outputs of the flip-flops. But the flip-flops change their state at the same time (that is, synchronously). This is clearly shown at 800 ns where all of the three change at the same time. The count goes directly from 111 to 000 without going from intermediate stages. We can also build counters from D-type flip-flops, operating as toggle flip-flops.
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