Inductive Reactance

The capacitors and inductors are two reactive components. This implies that they react, or oppose each other, changes in electrical variables.
A capacitor opposes, for example, or reacts, to any change in voltage level. Inductors, on other hand, “react” to changes in current flow. This reactive effect has a deep relationship with the frequency. When frequency of the applied voltage to an inductor is enhanced, the inductor’s opposition to AC flow of current increases. This all happens because the energy capable of being stored in the electromagnetic field of inductor (its inductance value) stays constant, but the time period of the applied AC-voltage gets decreases. when the AC time period is decreased, few energy is required from the inductor’s electromagnetic field to oppose the voltage alternations. Take this example, when it would take 10 times the energy to oppose 100 volts for 10 seconds than it would to oppose the same voltage for 1 second.

The same rule applies with an increase in the frequency amd decrease in time period of the applied AC. We can state this basic principle by saying that the reactance of an inductor increases with an increase in frequency. This “frequency-dependent” opposition to AC flow of current through an inductor is called inductive reactance. The inductive reactance (XL), as are impedance (Z) and resistance (R), is measured in terms of ohms. The equation for calculating the value inductive reactance is, or formula of inductive reactance is
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Capacitive Reactance

The Capacitors, like inductors, have a feature of frequency-dependent opposition to AC current flow called capacitive reactance (XC). When we apply AC voltage to a capacitor, it will charge and discharge in an effort to maintain a constant level of voltage. When frequency of the applied voltage to a capacitor is increased, capacitor’s opposition to AC current flow decreases. This is the main reason as to the amount of energy capable of being stored in the capacitor’s electrostatic field (it`s capacitance value) stays constant, but at the same moment the time period of the applied AC voltage decreases. it becomes pretty easy for the capacitor to fully absorb the charge of each half-cycle, as the AC time period decreases. In other point of view, it would require 10 times the capacity for a capacitor to charge for 10 milliseconds than it would for one millisecond. Therefore, the capacitive reactance decreases just when the frequency of an applied-voltage increases. Below is the equation for finding value capacitive reactance (Xc)
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Reflection Impedance

If we apply 120-volt AC, 60-hertz power to the primary of a power transformer with its secondary open, a very small current will flow through the primary winding. Only a small quantity primary current will flow because the inductive reactance of the primary winding is very high. However, if a load is then placed on the secondary winding
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Monostable Multivibrators

The pulse detector is categorized as a mono-stable multi-vibrator because it has only one stable state. By term stable, we mean to say a state of output where the device is able to latch or hold to forever, without any external prodding. A latch or a flip-flop, being a bi-stable device, can hold in one state either "set" or "reset" state for an in-definite period of time. Once it is set or reset, it will continue to latch in that state unless impelled to change by way of an external input. A monos table device, on the other end, has the only capacity  to hold in one particular state indefinitely. Its other state can only be held momentarily when triggered by an external input.

A mechanical analogy of a mono-stable device would be a momentary contact pushbutton switch, that spring returns to its ordinary (stable) state when pressure is removed from its button actuator. Likewise, a standard wall (toggle) switch is a bi-stable device. It can latch in one of the two modes: on or off. All mono-stable multi-vibrators are timed devices. That is, their unstable output state will hold only for certain lowest amount of time before returning to its stable state. With the semiconductor mono-stable circuits, this timing function is naturally achieved through the use of capacitors & resistors, making the use of the exponential charging rates of RC circuits. A comparator is sometimes used to perform comparison of the voltage across the charging or dis-charging capacitor with a steady reference voltage, and the on (off) state of output of the comparator used for a logic signal.
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There is another variation on a subject matter bi-stable multi-vibrators is the J-K flip-flop. Basically, this is a modified version of an S-R flip-flop with no ‘invalid or illegal" output stateshave a close look at the following diagram to see how this is achieved.  What used to be the S and R inputs are now known as the J and K inputs, respectively. The older 2-input AND gates have been replaced with 3-input AND gates, and 3rd input of each gate gets feedback from the Q and not-Q outputs. Now J-input will have effect only when it is reset, and permit the K input to have effect only when the circuit is in set. Say it differently, the 2 inputs are inter-locked, to use a relay logic term, so that they cannot both be activated at the same time. If the circuit is "set," the J input is inhibited by the 0 status of not-Q through the lower AND gate and if the circuit is in "reset," the K input is inhibited by the 0 status of Q through the upper AND gate.
When the J and K inputs are 1, however, something unique happens. Because of the selective inhibiting action of those 3-input AND gates, a "set" state inhibits input J so that the flip-flop acts as if “ J=O” while” K=l” when in fact both are 1. On the next clock pulse, the outputs will switch "toggle” from set (Q=l and not-Q=0) to reset (Q=0 and not-Q=1). Conversely, the "reset" state inhibits input K so that the flip-flop acts as if J=l and K=O when in fact both are 1. The next clock pulse changes the circuit again from reset state to set.  Note here that, if you can follow this logical sequence with the ladder logic equal of the J-K flip-flop. The end result is that the S-R flip-flop's "invalid" state is eliminated (along with the race condition it engendered) and we get a useful feature as an additional bonus: the ability to toggle between the two (bi-stable) output states with the every transition of the clock input signal. There is nothing such thing same as a J-K latch, only the J-K flip-flops. Without having the edge-triggering of the clock input, the circuit will continuously toggle between its 2 output states when both J and K were held high at 1, making it an astable device instead of a making  bistable device in that circumstance. If you want to maintain bistable operation for all pairs of input states, you must use edge-triggering so that it toggles only when you tell it to, one step (clock pulse) at a time. The block symbol for a J-K flip-flop is entire lot less alarming than its internal circuitry & just like the S-R and 0 flip flops, the J-K flip-flops come in 2 clock varieties i.e. negative and positive edge-triggered.
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Also known as the stairstep-ramp, or simply count the AID converter this is also very easy to understand but unfortunately suffers from several limits.Root idea is to connect the output of a free-running binary counter to the input of a DAC, and then comparing the analog output of the DAC with the analog input signal to be digitized and use the comparator's output to tell the counter when to stop counting and reset. The following plan shows the underlying idea:
As the counter counts up with each clock pulse, the DAC outputs a slightly higher (more positive) voltage. This voltage is then compared against the input voltage by the comparator. If the input voltage is greater than the DAC output, the comparator's output will be high and the counter will keep counting in normal manner. Ultimately, the DAC output will exceed in amount of the input voltage, causing the comparator's output to go low. This will lead 2 things to occur: first, the high-to-Iow transition of the comparator's output will make the shift register to "load" whatever binary count is being output by the counter, hence updating the ADC circuit's output.  Secondly, the counter will receive a lower signal on active-low LOAD input, making it to reset to 00000000 on the very next clock pulse. The effect of this circuit is to produce a ‘DAC’ output that ramps up to whatever level the analog input signal is at, output the binary number related to that level, and start over again. Schemed over time, it looks like this:
Note here that how the time between updates (new output values) changes depending on no matter how high the input voltage is. For low signal levels, closed-spaced updates are found. For higher signal levels, they are spaced further apart in time:
For many of the ADC applications, this variation in the updated frequency, that is, sample time will not be in acceptable range. the circuit's need to count all the cases from 0 at the beginning of each count cycle makes for comparatively slow sampling of the analog signal, places the digital-ramp ADC at a drawback to other the counter strategies.
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This tutorial explains about Serial-in, serial-out shift registers. These registers delay data by one clock time in each stage. They will store a bit of data for each of the registers. A serial-in, serial-out shift register may be 1 to 64 bits in length, longer registers or packages are cascaded.
Discussed Below is a single stage shift register which is receiving data and which is not synchronized to the register clock. The ‘data in’ at the D pin of the type D FF (Flip-Flop) does not change levels when the clock changes from low to high. You may want to synchronize the data to a system wide clock in a circuit board to improve reliability of the digital logic circuit.
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Reflection coefficients

The Reflection coefficients are based on concepts introduced in our childhood. Imagine the case when you throw a ball at the vertical stone wall. The ball having its incident power will travel towards the stone wall, hit the wall which will soak up some of its power and then the remaining power, reflected power, will cause the ball to bounce back towards you.
The ratio of (reflected power)/(incident power) is known as the reflection coefficient. The reflection coefficient is often represented by the Greek letter gamma (G).
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Bi-stable multi-vibrator contains two stable states, as indicated by the prefix “bi” in its name. Typically, one state is referred as set and the other as reset. The simplest bi-stable device, therefore, is known as a set-reset, or S-R, latch. In order to create an S-R latch, wire two NOR gates in such a way that the output of one feeds back to the input of another  and vice versa, like this: The Q and not-Q outputs are supposed to be in opposite states. It is "supposed to" because making both the Sand R inputs equal to 1 results in both Q and not-Q being O. Due to this reason, having both S and R equal to 1 is called an invalid or illegal state for the 5-R multi-vibrator. Otherwise, making S=1 and R=0 "sets" the multi vibrator in such a way that Q=1 and not-Q=O. Conversely, making R=1 and s=0 "resets" the multi-vibrator in the opposite state. When S and R are both equal to 0, the multi-vibrator's outputs "latch" in their prior states. Note here that how the same multi-vibrator function can be implemented in ladder logic, with the identical results:
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Types of Motors

You will come across many types of motors. People have been trying different ways to make a motor nearly as long as they have been messing with electricity. Here is a brief overview on some types of DC motors.

Brushless DC Motors

The brushless DC motors are cousins to the DC PM motor but instead of using brushes for commutation, they usually use some type of electronic control. To accomplish this, usually the inner side of the motor contains permanent magnets (where the armature is in the DC PM motor). This is known as rotor. The windings are on the outside and are referred to as the stator, or field windings.
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