The normal inputs of data to a flip flop (0, Sand R, or J and K) are specified to as synchronous inputs because they have ability to affect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. These additional inputs that are brought to your knowledge are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Normally, they're called preset and clear.
When the preset input is activated, the flip-flop will be set (Q=l, not-Q= O) without any regard of the synchronous inputs or the clock. When we activate the clear input, the flip-flop will be reset (Q=O, not-Q=l), regardless of any of the synchronous inputs or the clock. So, what will happen if we activate both preset and clear inputs? we get an invalid state on the output, where Q and not-Q go to the same state, just like as our old friend, the S-R latch! Preset and clear inputs find application when multiple flip-flops are ganged together at the same time to perform a function on a multi-bit binary word, and just a single line is required to set or reset them all at once.
The Asynchronous inputs can be engineered to be active-high or active-low. If they are active-low, it will cause there an inverting bubble at that input lead on the block symbol, the same happens in the negative edge-trigger clock inputs. In some occasions the designations "PRE" and "CLR" will be shown with inversion bars above them, in order to further represent the negative logic of these inputs.
0 comments:
Post a Comment