PHASE LOCKED LOOP

The main function of a PLL is to lock on to an input logical signal of any given frequency, even when the signals are distorted, or they are coming from a noisy background, & signal is mixed with some other signals having different frequencies. The essential components of a PLL are shown in the diagram below. The first stage is the phase detector. It receives 2 logic-level signals, one at the input to the PLL and the other fed back from its output.

The simplest phase detector is an exclusive-OR gate. This is proposed for square-wave signals with fifty% duty cycle. If the two signals are of the same frequency and in phase with each other, the output of phase detector is 0.

If the 2 signals are of different frequencies, the inputs to the ex-OR gate will not be equal and the output of the gate goes high. The greater the difference b/w the 2 signals, the more higher will be the output of the gate.

The output coming from the gate is passed through a low-pass filter for the purpose of averaging out the overall response. This smoothed output then goes to a VCO. The central frequency of this is set by resistors and a capacitor to be in the middle of the range that is to be detected, but changes on either side of this, depending on its input voltage - the signal from the phase detector by way of the low-pass filter.

When a signal is first sent to the PLL there will be less chance for it the same frequency as the VCO. The detector/filter, therefore, generates an output voltage. This will either increase or decreas ethe frequency level of the VCO to the moment when it locks on to the input signal. Therefore, the output of the PLL is of the same frequency as the original input signal. The significant difference is that the output from the PLL is a clean square wave and contains no noise and no signals of some other frequencies.

frequently a PLL contains an additional sub-circuit, placed b/w the VCO and the phase detector. This is a frequency divider. If it is made to divide by n, the PLL locks on with the VCO frequency n times that of the incoming signal. This is a technique of generating a high frequency signal from a low frequency but high-precision clock