SUCCESSIVE APPROXIMATION ADC

This is the method of addressing the shortcomings of digital ramp ADC and this is so-called successive-approximation ADC. It has the only change in its design is a very special counter circuit that is known as a successive approximation register. Instead to count up in binary sequence, this register counts by trying all values of bits that starts with the most-significant bit and ends at the least-significant bit. Throughout this counting process, the register monitors the comparator's output to look for whether the binary count is less than or more than the analog signal input, and thereby adjusting the bit values accordingly.

The process of counting of the register is same as to the "trial-and-fit" method of decimal-to-binary conversion. In that method various values of bits are tried from MSB to LSB in order to obtain a binary number that equals the original decimal number.  The benefit of this counting strategy is that it provides much faster results: the DAC output converges on the analog signal input in much larger steps than with the O-to-full count sequence of a regular counter.

Without displaying the inner workings of the successive-approximation register (SAR), the circuit looks like this: It is be noted that the SAR is normally capable of outputting the binary number in serial (one bit at a time) format, consequently eliminating the requirement for a shift register. designed over time, the operation of a successive-approximation ADC looks like this: keep in mind that how the updates for this ADC happen at regular intervals, that is not like the digital ramp ADC circuit.