RIPPLE COUNTERS

 The clock shown in diagram 22.5 is running at 1 MHz in the simulation of a 3-bit up-counter. Traces show the clock from top to bottom and A,B & C shows the output. At one mega hertz clock rates or less, we may ignore the propagation delays of  few nanoseconds.

 Figure 22.6 shows the result when we increase the clock rate by ten times and outputs are also plotted on 10 time scale. The Propagation delays are of more relative importance and we can observe them in the plots. 11 ns is a typical delay interval of the 74LS73 J-K flip-flop that is used in simulation . 

The plot shows that each stage changes state 11 ms after the output from the previous stage has gone low.  This shows up best after 800 ns, where all outputs are 1; then they all change to 0, one after the other First the clock goes low, then flip-flop A, then flipflop B and finally flip-flop C. The change from 1 to 0 continously ripple along the chain. This is the reason that make such a counter a ripple counter. The rippling action is also illustrated by the arrows in lines 5 and 9 in the diagram. The rippling action is even more observable in counters that have four or more than 4 stages. The table shown below presents the sequence of outputs in a ripple up-counter as the count changes from 111 to 000. The digits change from 1 to 0 in order that begins with the LSD on the right.

 

While varying from 7 to 0 the out put of counter goes very briefly through 6 and 4. This will not matter. For instance, if the clock is running at 1 Hz frequency, and the counter is supporting to drive an LED display that shows the number of seconds elapsed, inthis case we camnot be able to see the incorrect ‘6’ and ‘4’. The display dirctly changes from ‘7’ to ‘0’. We can have alogic circuit which is connected to the output, intended to detect, say, a ‘6’ output. This will easily respond to the brief but incorrect type of output. This may even cause it to initiate some other activity in the circuit at a given time when it not required to took place.

In the simulation a ripple counter was used as a appropriate method to provide inputs 000 to 111 to the logic network. However, when the counter input changed from 011 to 100 (that is, at 800 ns), it typically went through a stage 010. As it is visible from the plots at about 500 ns, this is an input which provides a low output from the network. Due to this there will be a low glitch on the output at 800 ns. The logic network fast enough in order to respond to the incorrect output.