Referring to the diagram below, note in the diagram that the gate is effectively placed close to the same potential as circuit common through resistor RG.
When there is no input applied, the gate voltage value (relative to circuit common) is zero. However, this does not lead to mean that the gate-to-source voltage is equal to zero. Consider that the source resistor (RS) is 100 ohms, and the drain current, which is the equal as the source current, is 15 milliamps. This 15-milliamp current will flow through RS would cause it to drop 1.5 volts, placing the source lead of the FET at a positive 1.5-volt potential ‘above circuit common.’ If the value of source is 1.5 volts more positive than the value of gate, it could also be mentioned that the gate is 1.5 volts more negative that of the source. (Is an 8-ounce glass, with 4 ounces of water in it, whether it is half-full or half-empty?)Ultimately, the level of gate-to-source voltage in this scenario is
-ve 1.5 volts. This also implies that the gate posses a -1.5-volt negative bias. If a signal voltage is applied to the input, leading the gate to become more negative, the FET will tend to less conductive (and more resistive), and vice versa. A JFET demonstrates maximum conductivity ( and minimum resistance), from the source to the drain, with no bias voltage applied to the gate.
MOSFETs are biased in ways that are similar to JFETs, except in the case of enhancement-mode MOSFETs. As mentioned before, enhancement mode MOSFETs are biased with a gate voltage having opposite polarity to their other FET counterparts. There are some enhancement-modes MOSFETs are designed to operate in both mode of operation. In general, FET provides the circuit designer with a greater degree of simplicity and more flexibility, due to their lack of inter-stage loading considerations
(the transistor stage having a high input impedance will not load down the output of a previous stage). This can also result in the need for fewer stages, and less complexity in many circuit designs.
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