Delta-Sigma ADC

The delta-sigma is one of the most advanced ADC technologies. In mathematics and physics, the capital Greek letter delta represents any difference or change, while the capital letter sigma used to represent summation, that is, the adding of multiple terms together. Sometimes this converter is shown by the same Greek letters in reverse order: sigma-delta.

In a converter design, the analog input voltage signal and the input of an integrator are connected, giving a voltage rate-of-change, or slope, at the output that corresponds the magnitude of input. The comparator compares this ramping voltage against ground potential (0 volts). The comparator performs as a sort of 1-bit ADC giving 1 bit of output ("high" or "low") depends on the integrator output that whether it is positive or negative. In The step comparator's

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SUCCESSIVE APPROXIMATION ADC

This is the method of addressing the shortcomings of digital ramp ADC and this is so-called successive-approximation ADC. It has the only change in its design is a very special counter circuit that is known as a successive approximation register. Instead to count up in binary sequence, this register counts by trying all values of bits that starts with the most-significant bit and ends at the least-significant bit. Throughout this counting process, the register monitors the comparator's output to look for whether the binary count is less than or more than the analog signal input, and thereby adjusting the bit values accordingly.

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DIGITAL RAMP ADC

Also known as the stairstep-ramp, or simply count the AID converter this is also very easy to understand but unfortunately suffers from several limits.Root idea is to connect the output of a free-running binary counter to the input of a DAC, and then comparing the analog output of the DAC with the analog input signal to be digitized and use the comparator's output to tell the counter when to stop counting and reset. The following plan shows the underlying idea:

As the counter counts up with each clock pulse, the DAC outputs a slightly higher (more positive) voltage. This voltage is then compared against the input voltage by the comparator. If the input voltage is greater than the DAC output, the comparator's output will be high and the counter will keep counting in normal manner. Ultimately, the DAC output will exceed in amount of the input voltage, causing the comparator's output to go low. This will lead 2 things to occur: first, the high-to-Iow transition of the comparator's output will make the shift register to "load" whatever binary count is being output by the counter, hence updating the ADC circuit's output.  Secondly, the counter will receive a lower signal on active-low LOAD input, making it to reset to 00000000 on the very next clock pulse. The effect of this circuit is to produce a ‘DAC’ output that ramps up to whatever level the analog input signal is at, output the binary number related to that level, and start over again. Schemed over time, it looks like this:

Note here that how the time between updates (new output values) changes depending on no matter how high the input voltage is. For low signal levels, closed-spaced updates are found. For higher signal levels, they are spaced further apart in time:

For many of the ADC applications, this variation in the updated frequency, that is, sample time will not be in acceptable range. the circuit's need to count all the cases from 0 at the beginning of each count cycle makes for comparatively slow sampling of the analog signal, places the digital-ramp ADC at a drawback to other the counter strategies.

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