The delta-sigma is one of the most advanced ADC technologies. In mathematics and physics, the capital Greek letter delta represents any difference or change, while the capital letter sigma used to represent summation, that is, the adding of multiple terms together. Sometimes this converter is shown by the same Greek letters in reverse order: sigma-delta.
In a converter design, the analog input voltage signal and the input of an integrator are connected, giving a voltage rate-of-change, or slope, at the output that corresponds the magnitude of input. The comparator compares this ramping voltage against ground potential (0 volts). The comparator performs as a sort of 1-bit ADC giving 1 bit of output ("high" or "low") depends on the integrator output that whether it is positive or negative. In The step comparator's
output is latched through a D-type flip-flop that is clocked at a high frequency rate, and fed back to another input channel on the integrator, in order to lead the integrator in the direction of a 0 volt output. The basic circuit looks like this:
output is latched through a D-type flip-flop that is clocked at a high frequency rate, and fed back to another input channel on the integrator, in order to lead the integrator in the direction of a 0 volt output. The basic circuit looks like this:
In the leftmost op-amp is the (summing) integrator. The next op-amp is the comparator in which the integrator feeds into, or 1-bit ADC. Next to it comes the D-type flip-flop, its work is to latch the comparator's output at every clock pulse, sending either a "high" or "low" signal to the next comparator that is at the top of the circuit. This last comparator is mandatory to convert the single-polarity OV/ SV logic level output voltage of the flip-flop into a +ve/ -ve voltage signal
That can be fed back to the integrator. If the integrator gives positive output, the first comparator will give output a "high" signal to the “0” input of the flip-flop. At the next clock pulse, this
210 Digital-Analog Conversion "high" signal will be output from the Q line into the non-inverting input of the last comparator.
The last comparator, considering an input voltage more than the threshold voltage of 1/2 +ve, oversupply in a positive direction, sending a full positive signal to the other input of the integrator. This positive feedback Signal tends to lead the integrator output in a negative direction. If that output voltage ever becomes negative, the feedback loop will send a signal (-V) to correct back around to the top input of the integrator to make it in a positive direction. This is the delta-sigma concept in action: the first comparator senses a difference between the integrator output and zero V9lts. The integrator sums the comparator's output with the analog input signal.
Functionally, this results in a serial stream of bits output by the flip-flop. The integrator will not tend to ramp either positive or negative, if analog input is 0 volts, except in response to the feedback voltage.
In this case, the flip-flop output will rapidly oscillate between "high" and "low," as the feedback system "hunts" back and forth, trying to keep the output integrator at 0 volts. If negative analog input voltage is provided, the integrator will have a tendency to ramp its output in a positive direction. Feedback has the ability to only add to the integrator's ramping by a fixed voltage fixed interval of fixed time, and as a result the bit stream output by the flip-flop will not be reasonably the same.
By supplying a larger -ve analog signal as input to the integrator, its output can be forced to ramp more steeply in the positive direction.
As the analog input signal increases in scale, so does the occurrence of 1 's in the digital output of the flip-flop: A parallel binary number output is obtained from this circuit by way of averaging the serial stream of bits together.
Variations can be made by employing multiple integrator stages and/or comparator circuits giving output more than 1 bit, but there is one concept that is common to all converters is that of oversampling. The process of Oversampling is that when multiple samples of an analog signal are taken by an ADC (a 1-bit ADC), and those digitized samples are averaged. The final result is an effective increase in the number of bits resolved from the signal. Or say in other words, an oversampled 1-bit ADC can perform the same job just like an 8-bit ADC having one-time sampling, although at a slower rate.
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