SERIAL IN SERIAL OUT SHIFT REGISTER

This tutorial explains about Serial-in, serial-out shift registers. These registers delay data by one clock time in each stage. They will store a bit of data for each of the registers. A serial-in, serial-out shift register may be 1 to 64 bits in length, longer registers or packages are cascaded.

Discussed Below is a single stage shift register which is receiving data and which is not synchronized to the register clock. The ‘data in’ at the D pin of the type D FF (Flip-Flop) does not change levels when the clock changes from low to high. You may want to synchronize the data to a system wide clock in a circuit board to improve reliability of the digital logic circuit.

The clear point illustrated above is that whatever "data in" is present at the D pin of a type D FF is transferred from D to output Q at clock time. Since the example of shift register uses positive edge sensitive storage elements, the output Q follows the D input when the clock transitions from low to high.

There is no ambiguity what logic level is present at clock time because the data is stable well before and after the clock edge. This is often the case in multi-stage shift registers. We are only concerned with the positive, low to high, clock edge. The falling edge can be ignored. It is easier to see Q follow D at clock time above. Since "data in" appears to changes at clock time t1 above, what does the type D FF see at clock time? The short over simplified answer is that it sees the data that was present at D prior to the clock. That is what is transferred to Q at clock time tl. The correct waveform is QC. At t1 Q goes to a “0” if it is not already zero. The D register does not see a one until time t2, at that time Q goes high.

Data present at D is clocked to Q at clock time, and Q can-not change until the next clock time, the D FF delays data by one clock period, provided that the data is already synchronized to the clock. The

The QA waveform is same as’ data in’ with only one clock period delay. A detailed look at what the input of type D Flip-Flop sees at clock time follows. If the "data in" is from another shift register stage, another same type D FF, it is easy to draw conclusions based on the data sheet information. Producers of digital logic make available information about their parts in data sheets, formerly only available in a collection called a data book