THE J-K FLIP-FLOP

There is another variation on a subject matter bi-stable multi-vibrators is the J-K flip-flop. Basically, this is a modified version of an S-R flip-flop with no ‘invalid or illegal" output stateshave a close look at the following diagram to see how this is achieved.  What used to be the S and R inputs are now known as the J and K inputs, respectively. The older 2-input AND gates have been replaced with 3-input AND gates, and 3rd input of each gate gets feedback from the Q and not-Q outputs. Now J-input will have effect only when it is reset, and permit the K input to have effect only when the circuit is in set. Say it differently, the 2 inputs are inter-locked, to use a relay logic term, so that they cannot both be activated at the same time. If the circuit is "set," the J input is inhibited by the 0 status of not-Q through the lower AND gate and if the circuit is in "reset," the K input is inhibited by the 0 status of Q through the upper AND gate.

When the J and K inputs are 1, however, something unique happens. Because of the selective inhibiting action of those 3-input AND gates, a "set" state inhibits input J so that the flip-flop acts as if “ J=O” while” K=l” when in fact both are 1. On the next clock pulse, the outputs will switch "toggle” from set (Q=l and not-Q=0) to reset (Q=0 and not-Q=1). Conversely, the "reset" state inhibits input K so that the flip-flop acts as if J=l and K=O when in fact both are 1. The next clock pulse changes the circuit again from reset state to set.  Note here that, if you can follow this logical sequence with the ladder logic equal of the J-K flip-flop. The end result is that the S-R flip-flop's "invalid" state is eliminated (along with the race condition it engendered) and we get a useful feature as an additional bonus: the ability to toggle between the two (bi-stable) output states with the every transition of the clock input signal. There is nothing such thing same as a J-K latch, only the J-K flip-flops. Without having the edge-triggering of the clock input, the circuit will continuously toggle between its 2 output states when both J and K were held high at 1, making it an astable device instead of a making  bistable device in that circumstance. If you want to maintain bistable operation for all pairs of input states, you must use edge-triggering so that it toggles only when you tell it to, one step (clock pulse) at a time. The block symbol for a J-K flip-flop is entire lot less alarming than its internal circuitry & just like the S-R and 0 flip flops, the J-K flip-flops come in 2 clock varieties i.e. negative and positive edge-triggered.