The clock shown in diagram 22.5 is running at 1 MHz in the simulation of a 3-bit up-counter. Traces show the clock from top to bottom and A,B & C shows the output. At one mega hertz clock rates or less, we may ignore the propagation delays of few nanoseconds.
Figure 22.6 shows the result when we increase the clock rate by ten times and outputs are also plotted on 10 time scale. The Propagation delays are of more relative importance and we can observe them in the plots. 11 ns is a typical delay interval of the 74LS73 J-K flip-flop that is used in simulation .
