Diagtam 12. 10 show the symbol used for the data-type (or D-type) flip-flop and the action of ehis flip flop is plotted in the graphs. For the purpose of clocked mode operation like this, the Set input (S) and Reset input (R) are held low. Buy there are few kinds of D-type flip-flop that do not have the R input.
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The graphs that are shown below are drawn on the basis of a simulator, modelling a 74LS74 D-type flip-flop. This clock is running at the frequency of 10 MHz and the time scale measures in nanoseconds. When The graph lowest it shows the output Q. The simulator is stepped manually so that it enables you to make the data input high or low when we desire.
The run of the clock commences with both D and Q low. We are making higher at 170 ms. At this instant of time the clock is high. Nothing will affect to the output in case the clock goes low. The Q will go high at the next rising edge of the clock. This occurs at the time interval of 250 ns. If we look the timing more closely, we will note that the rise in Q occurs slightly later than the rise in the clock. This is because there is the propagation delay of the flip-flop, here set to a typical value of 22 ns. Consequently, Q goes higher at 272 ns. Subsequent changes in D, at 540 ns, 640 ns and 880 ns, always appear at output Q at the next rising edge of the clock (also the propagation delay).
The D-type flip-flops are normally used for the purpose of sampling data at regular intervals of time. They then hold the data is processed, data is held unchanged. A very common example is its application at the input of digital-to-analogue converters
The Set and Reset inputs are used in the direct mode of operation of the flip-flop. The D-type-flip-flop is also called Preset and Clear inputs. When we set the input higher, the Q goes high instantly, without having any wait for the rising edge of the clock. Similar to this, Q goes low immediately the Reset input is made high.
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