FULL ADDER

The half adder is called half because it is in-complete. It cannot accept a carry-in Ci from a previous stage of the addition. The truth table related to the full adder is shown below. The addition of A and B is shown by the first four lines when the carry-in is zero. The values of A, B, S and Co are identical with the values contained in the half adder table. The last four lines of the table show the addition when carry-in is 1.

 

For S, in the table, the first four lines have an exclusive-OR output. The last 4 lines contains an exclusive-NOR output. When Ci is low the second exclusive-OR gate does not invert the output of the first one, so the output is exclusive-OR, and gives S for the first four lines of the table. When Ci goes at high level, the output of the first gate is inverted by the second gate, which results in resulting in exclusive- NOR, which gives S for the last 4 lines.

The Co column is representing a majority logic function. If the two or more inputs are higher the value of Co will be higher. We make use of majority logic but base it on four NAND gates. If we build the two exclusive-OR gates from NAND gates, the whole circuit would be in NAND gates. A gate is saved because the first exclusive-OR gate already has a NAND gate to provide the NAND of A and B so the output of this is used in producing the C_o. A total of 11 NAND gates are required in total. Although it is interesting to build a complex circuit from the basic SSI units, these are the circumstances where we started to make use of MSI devices such as the CMOS 4008 and the 74LS283 binary 4-bit full adders.