Dynamic RAM vs Static RAM

STATIC RAM

If we want to store a large amount of data we use an array of many flip-flops on a single chip. Such a large array is normally called a memory. Each flip-flop can store a single bit of data in it. Flip-flop has the capability to store data into it individually. The set or reset mode of flip flop, depends on whether the bit is a 0 or 1. This process is called writing, because the art of storing data is just like as writing information on a paper. Each flip-flop can also be read to check whether the data stored there is 0 or 1. One RAM chip may comtain several hundreds or thousands of flip-flops on it. For the purpose of writing to or read from any particular flip-flop among these, we require knowing its address.

 This is a binary number that describes its location within the array on the chipset. As we can write to or read from any flip-flop any time we want, we call this is random access. That is why a memory based on this principle is a random access memory, or RAM. SISO shift register is something different from this, which allows the bits of data to be read in the same order in which they were written.  Data written on a flip-flop remains there until we change it by writing new data in the same flip-flop, or the power supply is turned off and all data is lost in this case. Such a type of RAM is called static RAM, or SRAM.

DYNAMIC RAM

Now we talk about another type of RAM which is known as dynamic RAM, or DRAM. This RAM does not store the bits in flip-flops but as charges on the gate of MOSFET transistors. When we charge the gate, the transistor is on; if the gate has no charge, the transistor would be off. In case of DRAM, writing process consists of charging or discharging the gate. The Reading process consists of finding out whether the transistor is on or off. It is carried out by registering the output level (0 or 1) that it produces on the data line. The storage unit of a DRAM takes up very few space than a flip-flop, and hence more data can be stored on a chip. Reading and writing on the DRAM takes less time, which is an important feature in fast computers. There is problem with DRAMs that the charge on the gate leaks away. The data stored there compulsorily be refreshed at regular intervals.

Under the control of a clock running at about 10 kHz, the charge is passed from one transistor to another, and the amount of charge is topped up to the proper level at each transfer. The data is kept ‘on the move’, giving this type of memory the description ‘dynamic’. The need to refresh the memory regularly means that a substantial time of the computer’s operating time must be required for this purpose, and during this time we cannot read or write the RAM. For DRAM operating system is therefore more complicated than required for SRAM, which is available for using whenever we want.